Integrated circuits have become very complex, sometimes including millions of transistors on a single chip. Integrated circuits are therefore generally described by engineers in high level design languages, such as Hardware Description Language (HDL), and are converted automatically by a logic synthesizer into a gate level netlist, in accordance with user constraints on timing, power, area and other circuit attributes. The gate level netlist is then converted to a layout by a place and route (P & R) tool, also in accordance with user constraints.
Many elements of integrated circuits are synchronous elements which are timed by a clock signal. The faster the clock signal operates, the more operations are performed by the integrated circuit within a given time. There are, however, limitations on the speed at which circuits can operate and the clock signal should have a rate not greater than the fastest rate allowed by the circuit. Different circuits are therefore designed to operate at different clock rates, and some integrated circuits include sub-modules which operate at different clock rates. These circuits are referred to as multiple clock domain (MCD) VLSI circuits. A point at which circuits having different clock rates are interconnected is referred to as a clock domain crossing (CDC). Incorrect design of clock domain crossings may result in errors, known as “synchronization failures”, which may even cause the entire integrated circuit not to operate properly.
A paper titled: “A Comprehensive Approach to Modeling, Characterizing and Optimizing for Metastability in FPGAs”, by Betz et al., the disclosure of which is incorporated herein by reference, presents a function for calculating a mean time between synchronization failures (MTBF) of a CDC and requires that the MTBF be sufficiently long to avoid synchronization failures.
The high frequencies of VLSI circuits of the state of the art are so high that the decisions (e.g., optimizations) made by the logic synthesizer and the place and route (P & R) tool could dramatically affect the MTBF of a CDC, in a manner which could cause circuit instability.
A paper titled “Managing Synchronizer MTBF”, by Tim Davis, Aspen Logic Journal, Feb. 25, 2009, suggests that the human engineer designing the circuit manually add to the HDL circuit description constraints which limit the ability of the logic synthesizer and the place and route (P & R) tool to generate the CDC layout in an undesired manner.
A paper by R. Dobkin, R. Ginosar and C. P. Sotiriou, titled: “High Rate Data Synchronization in GALS SoCs,” IEEE Transactions on VLSI, 14(10), pp. 1063-1074, 2006, points out that some CDC synchronizers may require complex constraints which require substantial effort to generate.
US patent publication 2009/0235222 to Raje et al. describes a method for converting a circuit design for a programmable logic device (PLD) to a standard cell circuit design including automatically generating design constraints. The delay of a selected clock domain crossing is used as a hold time constraint for the paths crossing between the clock domains connected by the clock domain crossing, in order to prevent unwanted changes to the circuit.